ECE Lab Report
In this experiment, we constructed a circuit that was connected to a 7-panel writing board. The 6 inputs from the circuit were hooked up to the corresponding pins on the XS40 FPGA board. Then 6 outputs from the corresponding pins on the XS40 FPGA board were then connected to a ribbon cable that was connected to a computer. When the circuit was complete, we wrote a program in C++ to interface the hardware with the PC using its parallel-I/O port. The program was then improved to implement a calculator interface and performed mathematical operations. There were 15 different combinations on writing panel, which corresponded to 10 different digits, 4 different operands, and an equal sign.Writing panel: it is consisted of 7 metallic panels. Each panel is soldered to a wire, which is connected to the D-latch. The writing panel is used for the user to input the combination of the corresponding number, operand, and equal sign. 7474 D-latch: four chips were used during this lab because we need 7 inputs (Preset). Each panel from the writing board is connected to the PRE on the D-latch to set the state, '1' being used and '0' being unused. Three of four D-latches' CLRs were all connected to toget
The CLR' connections for the D-latch corresponding to outputs 1-7 are used to clear the state of the D-latched, and the PRE' connections are used to set the state, whether it's on or off, of the D-latches. When RESET is asserted while a panel is being scribed, it clears all the touched panels and starts a session for entering new combination. If panel 7 is touched without touching any other panel, following a RESET, nothing would happen because by not having touched any other panel implies illegal combination, which is then ignored by the computer. When each number has been successfully parsed, the computer is used to clear all D-Latches and reset the circuit for the next number to be inputted. Sending a momentary zero to Port B performs this reset. Port B is wired to the reset of each D-Latch, and by having to send this zero, all stored information is released. To assure the latches are usable for the next cycle a value of all ones, decimal value 255, is sent through Port B, which once again closes the latches. The circuit at this point is ready to accept input. her in order to clear the writing panel when it is grounded; moreover, all CPs and Ds were grounded. Flow Chart is on a separate piece of paper.
Some common words found in the essay are:
Data Value, D-latches RESET, XS40 FPGA, VHDL CONCLUSION, DESCRIPTION C++, DESCRIPTION Writing, RESET I/O, , D-latches' CLRs, DISCUSSION CLR', writing panel, equal sign, xs40 fpga board, fpga board, xs40 fpga, running total, input port, separate piece paper, 6 bits, flow chart, paper software, d-latches reset, operand equal sign, corresponding pins xs40, pins xs40 fpga,
Approximate Word count = 1143
Approximate Pages = 5 (250 words per page double spaced)
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